Self-aligned nanotube-nanowire phase change memory.

Low-voltage high-speed programming/erasing floating-gate memory device with gate- all-around polycrystalline silicon nanowire

Articles you may be interested in Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays Appl. Enhancement of programming speed on gate-all-around poly-silicon nanowire nonvolatile memory using self-aligned NiSi Schottky barrier source/drain High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory Appl. ...

Investigation of electromigration in In2Se3 nanowire for phase change memory devices

Coordination number model to quantify packing morphology of aligned nanowire arrays.

The average inter-wire spacing in aligned nanowire systems strongly influences both the physical and transport properties of the bulk material. Because most studies assume that the nanowire coordination is constant, a model that provides an analytical relationship between the average inter-wire spacings and measurable physical properties, such as nanowire volume fraction, is necessary. Here we ...

A Compact Thermal Model for Segmented Nanowire Phase-change Memory Cells

Organic electrochemical transistors based on a dielectrophoretically aligned nanowire array

In this study, we synthesized an organic electrochemical transistor (OECT) using dielectrophoresis of a carbon nanotube-Nafion (CNT-Nafion) suspension. Dielectrophoretically aligned nanowires formed a one-dimensional submicron bundle between triangular electrodes. The CNT-Nafion composite nanowire bundles showed p-type semiconductor characteristics. The drain-source current decreased with incre...